1. Field of the Invention
The present invention relates generally to a field effect transistor, and more particularly to a field effect transistor with epitaxial structures.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as the fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. The three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, and, accordingly, the channel region is more effectively controlled. The drain-induced barrier lowering (DIBL) effect and short channel effect (SCE) are therefore reduced. The channel region is also longer under the same gate length, and thus the current between the source and the drain is increased.
In another aspect, in order to further improve the devices performances, a strained-silicon technology has also been developed. The main principle in the strained-silicon technology is that strains are applied to predetermined regions within the field effect transistor which in turn make the field effect transistor work better by enabling charge carriers, such as electrons or holes, to pass through the lattice of the channel more easily. In detail, one main technology generally used in the strained-silicon technology is to dispose epitaxial structures with lattice constants different from that of the crystal silicon in the source/drain regions of the field effect transistors. The epitaxial structures are preferably composed of silicon germanium (SiGe), silicon phosphorous (SiP) and so forth, which have lattice constants different from that of the crystal silicon. Since the epitaxial structures have lattice constants larger or smaller than that of the crystal silicon, carrier channel regions adjacent to those epitaxial structures could sense external stresses and both the lattice structure and the band structure within these regions are altered. As a result, the carrier mobility and the performances of the corresponding field effect transistors are improved effectively. Additionally, because the epitaxial structures are generally disposed in the source/drain regions of the field effect transistors, and the surface areas of the epitaxial structures are often greater than those of the underneath fin-shaped structure, the epitaxial structures can therefore reduce the contact resistance between the source/drain regions and the corresponding contact plugs.
However, along with the continuous decrease in the size and dimensions of the field effect transistors, there are still some newly generated technological problems that need to be overcome, even though the non-planar transistor and the strained-silicon technology are already adopted. For example, for a field effect transistor fabricated through a replacement metal gate process, recesses used to receive epitaxial structures are often formed before the formation of the epitaxial structures and disposed in a fin-shaped structure at two sides of a dummy gate structure. However, because the recesses are formed by etching the fin-shaped structure, spacers disposed on two sides of the bottom of the dummy gate structure are often etched concurrently during this etching process. Accordingly, the epitaxial structures formed in the subsequent process may penetrate the spacers and directly contact with a dummy gate electrode of the dummy gate structure. In this situation, the epitaxial structures are inevitably electrically connected to the metal gate structure when the corresponding replacement metal gate process is completed, and the performance of the field effect transistor is worsened.